A highly secured small-area low power crypto accelerator design
Ng, Jun Sheng
Date of Issue2019
School of Electrical and Electronic Engineering
Today, encryption is a widely used protection measure in ensuring data security. It is implemented in data transmission and data storage system to protect the sensitive data from being exploited by adversaries. Only authorised personal with the secret key can access or read the data. Hence, the data remain safe as long as the secret key is hidden, even during the transmission process the encrypted data is extracted. AES (Advanced Encryption Standard) is a commonly used encryption algorithm in securing sensitive information. However, with cyber-physical-attack, the secret key of AES is potentially leaked out to the adversary through analysing the power dissipation and electromagnetic (EM) emanation during the encryption process. This kind of attack is also known as Side-Channel Attack (SCA), a well-known threat towards the hardware security in the modern society. In this project, small area and low power AES designs, known as Nano AES are designed and implemented. The design implemented is 3.1 times smaller and consumes 26% lesser power as compared to a standard AES design with the trade-off in computational speed. The Nano AES design is further scaled down by 24.4% in layout area and 10% in power consumption in the second design. After the design implementations, SCA is launched towards the AES designs to reveal their secret keys. Different power models had been used in the attacks to simulate the power consumption of the designs during the encryption process. The results were analysed and the effective power models were determined. At the same time, the vulnerability of the designs towards SCA was analysed too. The results of the SCA analysis showed that all the designs are still vulnerable towards SCA.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Final Year Project (FYP)
Nanyang Technological University