Setup and implementation of hierarchical scan insertion using the core wrapping technique
Date of Issue2018-10-23
School of Electrical and Electronic Engineering
Technical University of Munich
The rapid shrinking of the technology node from deep submicron levels to 90nm and below has allowed the complexity of the designs to increase without significantly increasing the chip size. Large designs are now posing many challenges to all design disciplines including design-for-test (DFT). For a System-on-Chip (SoC) with a few million flip-flops and multi-million gates, it has become extremely difficult to carry out DFT activities as full chip test pattern generation and simulation take enormous amount of time and computational resources, thereby decreasing the iterations in the entire design cycle. A hierarchical DFT methodology is employed, which helps in mitigating these problems by performing DFT activities like insertion of DFT logic, test pattern generation and simulation on a module (or IPs/Cores) rather than on the entire chip. To facilitate this, the modules/cores in the SoC are wrapped in such a way that testing of a module does not affect other modules and it itself is unaffected by the testing of other modules in the SoC. The patterns generated for the module are then retargeted from the SoC level. Core/module wrapping, scan chain insertion, automatic test pattern generation and pattern simulation are employed to implement this methodology. Mentor Graphics’ TessentScan is used for core wrapping and scan chain insertion while FastScan is used for generating test patterns. Cadence’s NCSim is used to simulate the test patterns. Employing this methodology has resulted in significant reduction in test pattern generation time and reduction in computational resources. This gain in time can now be utilized to analyze and improve the test coverage and focus on generating effective and fewer test patterns for lesser test time.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits