dc.contributor.authorJin, Yuhao
dc.date.accessioned2018-09-18T02:20:51Z
dc.date.available2018-09-18T02:20:51Z
dc.date.issued2018
dc.identifier.urihttp://hdl.handle.net/10356/76011
dc.description.abstractWith the growing focuses on the low power design, corresponding studies on low power circuits have become more and more popular. ALU is the basic and crucial component in microprocessors and a 4-bit low power ALU with logic and arithmetic functions is designed. This dissertation focused on the designs of fundamental units and the structure of ALU itself. The simulation, comparison and analysis of existing logic and arithmetic units have been done, including logic AND gate, logic OR gate, logic XOR gate, logic NOT gate, multiplexer, full adder, multiplier and so on. Several techniques have been used for low power design in this dissertation, which are passtransistor logic(PTL), modified circuits based on PTL, non-full-swing circuits, powergating, multiple supply voltages and algorithms including Wallace Tree and the calculation of optimal multiple supply voltage. The design and simulation are based on Cadence/Virtuoso software using schematics on transistor level. In addition, the circuits in this dissertation use TSMC’s 40nm technology and have been designed in static logic style.en_US
dc.format.extent82 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleLow power ALU designen_US
dc.typeThesis
dc.contributor.supervisorLau Kim Teenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US


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