Common-mode voltage reduction for 2-level voltage source inverter in parallel
Date of Issue2018-09-11
School of Electrical and Electronic Engineering
Pulse-Width-Modulation (PWM) control algorithms are commonly used in AC motors. However, in some cases the PWM itself may cause the bearing failures in electric drives, for which the common-mode voltage and current could be accounted. To reduce the common-mode voltage (CMV), both passive and active methods can be used, but active methods can be utilized without increasing the cost or adding the weight of the system. Besides, parallel inverters can provide more flexibility and reliability than single inverter in application. Based on this topic, the dissertation focuses on the effort of reducing the CMV in parallel inverters by using active methods, which are about the improvement from PWM. Following the methods used in single inverter, the dissertation further explores the possibility of generating a new method based on SVPWM to minimize the CMV in parallel inverters. To accomplish the goal, the dissertation reviews the aspects that should be concerned about for parallel inverters, including control methods and the loop current. Based on the parallel topology, a zero common mode voltage pulse width modulation (ZCMV-PWM) is proposed and the detail of its theory is presented, including the errors and adjustment when deducing this method. Finally, all the control methods are successfully verified by MATLAB/SIMULINK in different models built by the dissertation. And the results of them are taken to make comparison in the point of CMV reduction, quality of output current and loop current. The conclusion is that among the three control methods, which are SVPWM, AZSPWM1 and ZCMV-PWM, ZCMV-PWM performs the best result in CMV reduction and quality of output current, but not in the perspective of loop current.
DRNTU::Engineering::Electrical and electronic engineering