dc.contributor.authorKaur, Karandeep
dc.date.accessioned2018-01-03T07:24:12Z
dc.date.available2018-01-03T07:24:12Z
dc.date.issued2018
dc.identifier.urihttp://hdl.handle.net/10356/73135
dc.description.abstractThe Delta Sigma Analog to Digital Converter is the accurate means to convert an analog voltage into the representable data in the digital form. The method to convert data from Analog to Digital form through Delta Sigma ADC is accurate because it uses the oversampling technique, decimation, noise shaping and filtering to reduce the quantization noise and obtain a high resolution with an improved SNR. The architecture of Delta Sigma ADC modulator consists of Difference Amplifier, Integrator and Comparator. In principle of operation, the output of the modulator is feedback to the difference amplifier by a DAC. Each block in the ADC has an important role. These blocks are composed of mixed signal structures which consume a lot of power to do the signal processing in voltage domain. It has been investigated that the amplifier structures used in these blocks are the most power consuming circuits [1]. For the thesis work, a Low voltage Delta Sigma ADC designed by Infineon Technologies, Villach, Austria has been taken as the reference. In their design work, classical folded cascode operational transconductance amplifier has been used which provides an overall supreme quality performance of the ADC. The dissertation is based on investigating various topologies of amplifier circuits used in the integrator that could potentially reduce the power consumption of the Delta Sigma ADC. In an attempt to achieve this, Inverter based amplifier structures are considered using 120 nm CMOS technology. The work in dissertation discusses two design approaches. The first approach deals with Integrator that is build using Two Stage Fully Differential Inverter based Amplifiers. The other approach is based on Pseudo Differential Inverter based Amplifier, where a simple digital inverter is used with the separate biasing circuitry. In the first approach, two pair of inverters at the input stage ensures an increase in transconductance value and a high gain bandwidth product. The use of switch capacitors in both structures allows maximum differential input signal. A dedicated common mode feedback has been designed for both the approaches which are discussed in section 3.3 and 3.4. Further, a comparison has been made with different approaches and it is observed that with operational frequency of 62.5 kHz and oversampling ratio of 256, the system with folded cascode OTA achieves SNDR of 91.66 dB followed by ADC using fully differential inverter based amplifier getting an SNDR of 90.14 dB and for pseudo differential amplifier SNDR obtained is 87.88 dB. However, the average current consumption by system using Inverter based amplifiers is less than half of the average current consumption by folded cascode amplifier. This is discussed more in section 6.1.en_US
dc.format.extent82 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleDesign of CMOS inverter based amplifier for delta sigma ADC based smart sensor readoutsen_US
dc.typeThesis
dc.contributor.supervisorHelmut Graeben_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Integrated Circuit Design)en_US


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