3D interconnect-based segmented bus architecture modelling and exploration
Date of Issue2018-01-03
School of Electrical and Electronic Engineering
The communication and memory organization in system on chip are a major source of energy consumption. Future sub-10 nano-scale process and interconnect technologies will lead to higher performances but also to an increased energy bottleneck. To obtain high bandwidth, several solutions have been explored at the architecture level including crossbars and Network-on-Chip (NoC) routers. They come at a high cost in energy. The segmented bus architecture concept offers a potential way to considerably overcome this issue, for a given bandwidth requirement. Only the segments which are required to transfer the data are activated, thus isolating the activity. The partitioning of the bus is done by use of switches and the data is routed by controlling these switches. However, the device and circuit exploration for the switch implementation has been limited to CMOS style options in the state-of-the-art. This thesis proposes, to explore the use of IGZO TFTs based switches in the Back End of Line (BEOL) in such a segmented bus architecture for transmission between the processing system and their working memories. As a second part of this research, the three-dimensional (3D) integration topology in addition to two-dimensional integration in the x and y plane was explored. Also, the basic pseudo CMOS inverter design was modified to incorporate control transistors. In the end, a reference comparison in terms of area, energy, and delay was made with N14 FinFET technology. For confidentiality concerns, all the units reported in this report are normalized arbitrary units rather than the actual units and also the specific application has been omitted.
DRNTU::Engineering::Electrical and electronic engineering