Coding and signal processing for NAND flash memory
Chaudhry, Adnan Aslam
Date of Issue2017
School of Electrical and Electronic Engineering
NAND flash memory is a ubiquitous storage medium which has revolutionized the non-volatile memory industry by offering large storage capacity, high data throughput, fast read-response time and low power consumption. This has become possible mainly because of the advanced manufacturing processes, which have pushed the device scaling to its limits, and progressive read/write methods, such as the multi-level-cell (MLC) technology that enables multiple bits to be stored over a single memory cell. As the ash memory cells are integrated closer to each other, several channel impairment effects have emerged, which tend to degrade the reliability and endurance of ash memory system. This thesis is devoted to the design and analysis of new coding and signal processing solutions that can improve the reliability and endurance of the NAND flash memory. This thesis first investigates the non-stationary and asymmetrical behavior of major channel impairment effects in a model-based NAND ash channel, and presents optimization methods to adjust the read and write voltage levels to adapt to this non-stationary flash channel. The proposed optimization scheme is able to determine the write voltage levels that minimize the channel raw error probability throughout the operational lifetime of NAND flash memory, for different program/erase (PE) cycles and data retention time. Next, to enhance soft LDPC decoding performance while minimizing complexity, a novel entropy based quantization scheme is introduced to design the read voltage levels. Then, by joint read and write voltage signal optimization, the decoded error-rate performance is minimized and the decoding convergence speed is also improved. In NAND flash memory, the data retention noise induces cell voltage down-drift due to charge leakage and causes catastrophic decoding failure due to outdated bit boundaries. To recover from the retention noise-induced decoding failure, this thesis presents a two-stage retention-aware belief-propagation (RABP) decoding scheme. The most prominent advantage of this approach compared to the prior art is that new channel estimation which requires time- and power-consuming memory sensing operations can be avoided. In RABP decoding, the probable victim cells are determined with the help of read-back voltage signal and the decoded bit decision. For such suspected victim cells, their log-likelihood-ratio (LLR) regions are modified in such a way as to absorb the effect of cell voltage downshift caused by retention noise, and then a second round of BP decoding is performed afresh, often with decoding failure recovery. Furthermore, leveraging on the RABP decoded bit-error pattern, this thesis further develops a decision-directed channel update algorithm to re-estimate the latest cell voltage distribution parameters. Cell-to-cell interference (CCI) is yet another well-recognized source of errors in new generation NAND flash memories. This thesis exploits the data-dependent nature of CCI and proposes three post-processing schemes for its mitigation. The main idea is to remove (clean) the CCI component from the interfering cells before CCI cancellation from the victim cell. The proposed detection schemes are shown to outperform the existing CCI cancellation schemes. As the LDPC code is becoming the mainstream error-correcting code for NAND flash-based data storage, the application of iterative BP decoding incurs long processing latency which threatens to overshadow the benefits of NAND flash technology. Thus, LDPC codes for flash memories are desired to have fast decoding convergence so as to minimize the memory-read latency. This thesis investigates and presents various novel fixed and dynamic BP schedules which not only expedite the convergence of BP decoder, but also improve the system error-rate performance.
DRNTU::Engineering::Electrical and electronic engineering