System level simulation of a high power density point-of-load (pol) converters
Ang, Liang Sheng
Date of Issue2017-05-12
School of Electrical and Electronic Engineering
With the advancement of technology, many people have moved away from the traditional means of information storage, and rely on cloud services. In order to meet the soaring demand of storage spaces, telecom servers and data centers have been growing at an alarming rate. The rapid expansion and continuous rising demand for higher-performance server technology, has inevitably been consuming large amount of electrical energy. With the intervention of rising energy prices and environmental awareness, drivers are shifting towards an efficient energy transmission and distribution. Point-of-load (POL) converters are one such technologies used within data centers’ system board to maximize system efficiency. It is used to step voltages down from 48V to 3.3V and below to operate the servers cards in the servers’ rack. While it is agreed that high power density and efficiency can be achieved by wide bandgap power devices like Gallium Nitride (GaN) transistors, the boundary is not known. Therefore, in this report, a system level of a non-isolated direct current to direct current (DC-DC) buck converter is studied. A basic converter loss model of synchronous current mode (SCM) modelling followed by an improved modelling will be presented to study the losses of a buck converter. From the SCM model, it is observed that the bulk of losses come from the low side of the GaN transistor, with an efficiency of 82.51% at switching frequency of 300KHz. An additional function of diode emulation mode (DEM) modelling is implemented to study the possibility of reducing the low side switching loss. The DEM is found more useful at lower switching frequency where efficiency is observed to improve slightly from 31.49% to 31.71% at 100KHz.
Final Year Project (FYP)
Nanyang Technological University