Time optimal supervisory control of discrete event systems
Ahmad Reza Shehabinia
Date of Issue2017
School of Electrical and Electronic Engineering
This thesis focuses on the time-related performance objectives in supervisor synthesis of discrete event systems (DES). With this purpose in mind, we exploit the finite-state timed-weighted automaton as the modeling formalism. First, we present the concept of throughput to evaluate the time-performance of systems with cyclic behaviors. We formulate the supervisory synthesis problem ensuring both logic correctness and optimal throughput. After showing the existence of the supremal controllable sublanguage with maximum throughput, an algorithm is provided to compute such a supervisor. In the sequel, we model an operational and scheduling problem under multiple job deadlines, where each job is represented by a finite language and has to be completed within a finite period. The first step is to compute the supremal controllable job satisfaction sublanguage where all jobs and deadlines are met. In the case of nonempty supremal sublanguage, by adding proper delays to controllable transitions, we seek for one of the maximal controllable sublanguages that ensure the minimum total job earliness. If the supremal sublanguage is empty, we will relax some of the job deadlines, and compute a maximal controllable minimum-earliness.
DRNTU::Engineering::Electrical and electronic engineering::Control and instrumentation::Control engineering