Copper nanowires bonding for three dimensional interconnections
Chun, Shu Rong
Date of Issue2016-11-01
School of Materials Science and Engineering
GLOBALFOUNDRIES Singapore Pte. Ltd.
Over the past few decades, the semiconductor industry has been advancing by increasing transistor density on a microchip through continuous device scaling based on the technology roadmap driven by Moore’s Law. However, new physical phenomena at scaled dimensions and fundamental limitations in material properties are pushing the limits of existing planar devices. Moreover, interconnect delay, bandwidth and power dissipation are increasingly dominating the integrated circuits’ (IC) performance. Hence, a paradigm shift from the present IC architecture is needed to overcome the saturation in chip performance. Three dimensional (3D) integration has emerged as one of the promising techniques to overcome Moore’s Law, by replacing long horizontal wires with short vertical interconnects. This has resulted in smaller form factor, a reduction in RC (resistance-capacitance) delay and allows integration of heterogeneous systems with diverse functionality catering to “More than Moore” technology. However, 3D packaging which involves stacking of devices through the use of solder bumps or solder capped copper (Cu) pillar bumps, is facing challenges due to scaling down and reliability issues. In this work, fabrication of Cu nanowires (NWs) arrays coupled with thermocompression bonding is proposed as an alternative to existing 3D interconnection approaches. To explore the feasibility of adopting this alternative 3D interconnection, main emphasis is placed on the process development of the Cu NWs arrays on Si substrate and characterization of these bonded NWs arrays. The diameter of Cu NWs can be controlled by varying the anodization voltage, electrolyte type or pore widening duration during the fabrication of the porous alumina template. Growth of Cu NWs with preferred texture can be obtained by manipulating the electrodeposition conditions such as voltage and temperature. The use of different metal interlayers on the substrate influences the NWs density and subsequent processes. Characterization of the Cu NW revealed smooth and continuous morphology with preferred crystal growth orientation in  direction. The second part of the research focuses on the bonding of Cu NWs arrays. At low bond temperature of 200ºC, NW-Film and NW-NW bonding exhibit higher average shear strength than that of Film-Film bonding. However, scanning electron microscope (SEM), transmission electron microscope (TEM) and electron energy-loss spectroscopy (EELS) characterizations revealed that the Cu NWs have transformed into Cu oxide nanotubes. Further investigations show that the transformation was a result of Nanoscale Kirkendall Effect due to the low vacuum environment during bonding. Different annealing treatments on the NWs arrays also revealed that multiple voids form initially in the Cu NWs, with further growth through surface diffusion of Cu atoms along the voids’ surface which eventually leads to a hollow core. To overcome Cu oxide nanotube formation, another set of experiments was carried out using a commercial bonder with a high vacuum environment. Experimental results show that Nanoscale Kirkendall Effect can be suppressed. Moreover, increasing bond pressure or bond temperature resulted in a greater average shear strength and lower specific contact resistivity. Given an adequate NW density and bond pressure, the NWs are able to interlock with one another which increases the contact area between the NWs arrays, thus enhancing Cu interdiffusion. NWs bonding at 200ºC resulted in a continuous film with indistinguishable bond interface. TEM EELS mapping analysis shows that the bond nature is mainly Cu with small amount of oxygen distributed evenly across the bonded area. In conclusion, high density Cu NWs arrays on Si substrate can be achieved by optimizing the alumina anodization condition and electrodeposition of the Cu NWs. Using the Cu NWs as a bonding medium, Cu-Cu bonding can be achieved at a low temperature of 200ºC, which is desired for compatibility with back-end-of-line (BEOL) processing conditions. Moreover, growth of NWs arrays using anodized alumina template method allows patterning into small columns with flexibility in adjusting the interconnect pitch. Thus, Cu NWs arrays coupled with thermocompression bonding may be an alternative 3D interconnection approach to overcome the challenges in process integration.