Design of low power fractional-N phase locked loop for FMCW radar application
Date of Issue2016-08-16
School of Electrical and Electronic Engineering
High performance digital phase locked loops (DPLLs) have been proposed as alternatives to traditional phase locked loops (PLLs) based on analog charge pump. DPLLs offer several advantages over their analog counterparts. CMOS technology scaling also favors digital circuits over their analog counterparts. Despite offering significant advantages in area, manufacturability and programmability, the performance of DPLL is limited by performance of its key building blocks including time to digital converter (TDC), high resolution digital controlled oscillator (DCO) and high speed counter in counter-assisted DPLL architecture. In addition, frequency prescaler/divider is another indispensable component in high frequency phase locked loop (PLL) implementations and a major source of power consumption. In this report, each of the building blocks of DPLL is studied and both circuit level and architecture level innovations and implementations are proposed for low power DPLL implementation.