High speed data link for 3DICs
Aung, Myat Thu Linn
Date of Issue2016
School of Electrical and Electronic Engineering
Panasonic, Singapore; Global Foundary
The transistor scaling predicted by Moore's Law has driven the development of the semiconductor industries for many decades. As the lithography process approaches to its limit, research and development cost for a new technology node starts to increase as well as the cost of fabrication. As the incurred development time becomes longer, the rate of transistor scaling starts to decline. With 3D integration, there are more rooms to allocate transistors and thus, it improves the transistor counts critical to maintain the scaling trend. Moreover, due to the closed proximity of the circuit blocks in vertically integrated chips, the data bandwidth improves while power consumption and latency reduces. The testament of these benefits can be found in latest AMD's High-Bandwidth-Memory (HBM) achieving three times more bandwidth per watt. The introduction of HBM also solves the performance bottleneck in DRAM bandwidth which limits the GPU performance growth. In HBM, DRAM cores are stacked vertically and connected through through-silicon-via (TSV) and micro-bumps and it provides up to 3.5× bandwidth of the one DRAM chip in the very same footprint. Therefore, 3D integration is proved to be important not only to keep up with the Moore's law but also to catch up with the ever increasing bandwidth requirement from the advanced processor. The interposer technology also known as 2.5D integration provides high-speed channels between a processor and HBM within a short distance which could never achieve in the board level integration. There are several issues to address to make this 3D and 2.5D integration possible. When more and more dies are integrated together, the total system yield reduces. Moreover, interconnects (especially TSV and direct bondings) reliability remains a challenge. In 2.5D silicon interposer technology, the line width of high-speed linkages is very small causing high insertion loss to the signal. These are the issues discussed in this thesis. First of all, alternative interconnects technologies known as proximity communications in vertically stacked dies, opposed to TSV and Cu-Cu direct bonding, are thoroughly discussed and compared in terms of their feasibility, performance and methods used in the inductive coupling interconnect (ICI) and the capacitive coupling interconnect (CCI). Based on the findings, two designs in capacitive coupling scheme are proposed in this thesis. In the chapter 2, the possibility of simultaneous bi-directional signaling with CCI is studied and the novel electrodes and transceiver designs are proposed. This scheme is possible by the proposed interconnect in three cascaded capacitors configuration which ultimately creates multi-level voltages to allow simultaneous bi-directional signaling. The noise margin of the channel is measured to be 200mV when tested in the pseudo-3D interconnect structure. The transceiver is able to transmit and received 1.5Gbps simultaneously achieving the effective data rate of 3Gbps. In the chapter 3, the crosstalk among capacitive coupling electrodes is addressed. The crosstalk issue is well-known in CCI scheme and previously, two designs had been reported in the literature to address the issue. In contrast to the previous designs, the new proposed hybrid-CCI array design achieves not only crosstalk cancellation but also improves interconnect density and energy per bit. In the chapter 4, it is where the capacitive coupling communication meets with one of the 3D physical channels; Cu-Cu face-to-face thermal compression bonding. Here, the possibility of using the Cu-Cu bonded channel either as an ohmic or a capacitive coupling is explored. A dual-mode transceiver architecture and design is proposed to switch the transmission mode from ohmic mode to capacitive coupling mode when the Cu-Cu thermal compression bonding failed. In this way, the yield of Cu-Cu bonding can be improved. Lastly, in 2.5D high-speed data link, multi-taps de-emphasis or pre-emphasis driver is utilized to compensate for the frequency dependent high insertion loss. The conventional multi-taps designs use a lot of silicon area and consume huge power consumption for the emphasis coding. A compact size low power RC-modulated de-emphasis voltage mode driver which has 3-taps equivalent is introduced. Taps extension is done by charging the storage capacitor during the period of consecutive bits is transmitting and the de-emphasis strength is modulated by the resulting voltage in the capacitor itself. By doing so, the amount of hardware required for de-emphasis coding is minimized and the pre-driver switching activity is reduced as well as the dynamic power consumption. The designed de-emphasis strength resolution is up to 5.1dB. It is able to drive up to 10Gbps on a 2cm long micro-strip line on a silicon interposer. The driver, pre-driver and de-emphasis circuits consume 2.37mW at 10Gbps speed with full de-emphasis strength according to the post layout simulation.