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      A grid synchronization PLL method for distributed voltage unbalance compensation in an islanded microgrid

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      FYP Final Report_ChenYihang.pdf (2.055Mb)
      Author
      Chen, Yihang
      Date of Issue
      2016
      School
      School of Electrical and Electronic Engineering
      Abstract
      This project focus on improving the compensation of voltage unbalance in an islanded Microgrid, and includes two main steps. Firstly, by referring to the currently methods, a two-level control scheme will be built, which generates an unbalance compensation reference (UCR) in secondary control level and feeds it to local controller in primary level. Moreover, this project will consider the situation where some new distributed generators (DG) are immediately joined into the grid, leading to large overshoot or undershoot power. In order to decrease this impact, a grid synchronization phase-locked loop (PLL) method will be used.
      Subject
      DRNTU::Engineering
      Type
      Final Year Project (FYP)
      Rights
      Nanyang Technological University
      Collections
      • EEE Student Reports (FYP/IA/PA/PI)

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