A 65nm CMOS operational amplifier for analog/mixed-signal circuit applications
Date of Issue2016
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
Operational amplifiers (op-amps) are vital parts in most of the analogue circuits. For the LCD technology, a column driver buffer is the last and important stage. Designs based on an innovated concept are proposed and simulated using UMC 65nm technology in this work. The new single-stage single-pole-system op-amp can achieve a DC gain of 70 dB, GBW of 1.3 MHz, phase margin of 70°, SNR of 78 dB and power consumption of less than 15 μW over 150 pF-15nF capacitive load. The proposed designs are also compared with different benchmarks such as differential pair op-amp and nested-current-mirror op-amps under same condition. The parameters such as DC gain, bandwidth, slew rate, noise, SNR, small-signal FOMS, large-signal FOML and NEF (noise-efficiency factor) are compared. The simulation results have validated that proposed design has key advantages of GBW enhancement, good slew rate improvement, good FOMS and FOML. The circuit system is biased under current source to maintain constant transconductance as well as bandwidth against the variation of process, supply voltage and temperature.
Final Year Project (FYP)
Nanyang Technological University