dc.contributor.authorBian, Jia Kun
dc.date.accessioned2016-05-20T05:25:56Z
dc.date.available2016-05-20T05:25:56Z
dc.date.issued2016
dc.identifier.urihttp://hdl.handle.net/10356/67773
dc.description.abstractThis report discusses the design and characterization process and result of a novel SRAM: Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and instantly, the developed NIHE SRAM can be used to store highly confidential information. The first part of the report will review the conventional 6T SRAM design methodology and its figures of merit. In the second part, the NIHE SRAM cell operation will be discussed first, followed by the simulation result and analysis. Finally, the report will present the optimized version of NIHE SRAM cell’s layout. The NIHE SRAM cell was developed using Global Foundry 65nm technology.en_US
dc.format.extent55 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineeringen_US
dc.titleNon-imprinting high-speed erase SRAM IC design for low-power operationen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorGwee Bah Hweeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US


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