Time mode analog-to-digital converter
Hor, Hon Cheong
Date of Issue2016-02-11
School of Electrical and Electronic Engineering
Centre for Integrated Circuits and Systems
Fully digital Analog-to-Digital Converter (ADC) and digitally assisted ADC has gained popularity in recent research works. The continuous scaling in CMOS technology has prompted designers to look for ADC architecture that is highly digital intensive with minimal analog circuitry. Time Mode ADC appears as an attractive solution due to its more digital intensive topology. As transistor’s gate delay reduces along with scaling in CMOS technology, the resolution and speed of Time Mode ADC also improve along with the advancement in modern CMOS technology. There are two popular types of Time Mode ADC, namely the Voltage-Controlled-Oscillator (VCO) based ADC and the Integrating ADC. The VCO-based ADC works by first converting analog input voltage to frequency/time information by a VCO, where the frequency/time information is subsequently converted to digital code using a time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottleneck for Time Mode VCO- based ADC. In the first part of this research work, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. The main idea of K-locked-loop is to use local feedback in the voltage-time domain for VCO nonlinearity suppression. To the best of the author’s knowledge, this is the first ever proposed feedback system in the voltage-time domain. A 10-bit, 2MS/s K-locked-loop VCO ADC has been modeled using SIMULINK tool in Matlab as a proof of concept. In addition, an AMS model is constructed to further verify the concept of K-locked-loop at the transistor level. Through analysis, the non-ideal effect will be discussed in this thesis.