Design of minimum energy driven ultra-low voltage SRAMs and D flip-flop
Date of Issue2015
School of Electrical and Electronic Engineering
The aggressive CMOS technology shrinking driven by cost reduction, performance improvement and power minimization enables integration of billions of transistors onto a single chip. State-of-the-art System-on-Chips (SoCs) incorporate more cores, larger capacity caches and more application-specific hardware accelerators, resulting in significant increase of power density. To reduce power and improve energy efficiency, ultra-low voltage operation is widely employed. By lowering the supply voltage from nominal level to near or beneath transistor’s threshold voltage (known as near-/sub-threshold operation), the power is substantially suppressed and the energy efficiency is optimized. However, various challenging issues including high process-voltage-temperature (PVT) variation sensitivity and lack of systematic design methodology exacerbate the utility of ultra-low voltage circuits. New design methodology with minimum energy consideration to enhance performance, combat variability and suppress leakage is worthy of extensive and in-depth explorations. In the thesis, the characteristics of transistors at near-/sub-threshold region are studied and their impact on energy consumption is investigated. Based on that, ultra-low voltage circuits with improved performance, enhanced variation-resilience and high energy/energy-delay efficiency are developed. The main goal of the research is to explore and demonstrate optimal solutions of Static Random-Access Memory (SRAM) and D Flip-Flop (DFF) circuits in energy or energy-delay space and overcome the limitations imposed by ultra-low supply voltage. Specifically, the outcomes are demonstrated through an ultra-low voltage 9-transistor (9T) single-port SRAM, a near-threshold 12-transistor (12T) dual-port SRAM and an ultra-low voltage, energy-delay-efficient 16-transistor (16T) DFF: 1) As preliminary work, energy efficiency analysis of single-port SRAM utilizing multi-threshold CMOS (MTCMOS) technology is presented. The work investigates various device combinations and reveals the optimum device selection for the best energy efficiency from a MTCMOS perspective. 2) A 9T SRAM macro is developed with MTCMOS technology to enhance read performance and at the same time minimize leakage. In the 9T SRAM cell, a 3T-based novel read port is proposed to equalize read bitline (RBL) leakage and improve RBL sensing margin. To optimize energy efficiency, a miniature Content-Addressable-Memory-assisted (CAM-assisted) circuit is integrated to conceal the slow data development after data flipping in write operation and therefore enhance the operating frequency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable down to 0.26 V. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement. Energy efficiency is enhanced by 29.4% between 0.38 V ~ 0.6 V. 3) A 12T dual-port SRAM is proposed to suppress disturb at the common-row-access mode and improve read-ability, write-ability and cell stability. The novel dual-port SRAM cell significantly relaxes the probability of suffering disturb, increases the resilience against disturb and extends the operating voltage to near-threshold region. In addition, hierarchical bitlines and virtual ground schemes are employed to further improve performance and leakage of the SRAM circuit. A fabricated 16 kb 12T dual-port SRAM circuit shows successful dual-port operations down to 0.4 V at the common-row-access mode. 4) A 16T DFF with a low energy-delay product for sub-threshold applications is presented. The device count of the proposed DFF is minimized by eliminating the clock buffer and replacing transmission gates with pass gates. To reduce the Clock-to-Q delay and improve variation resilience, two charge pumps and inverse-narrow-width-effect-aware sizing strategy are utilized, improving the performance by 23%. The fabricated DFF is fully functional down to 0.18 V and shows an energy-delay product of 13.1 pJ•ns at 100% data activity, achieving an improvement of 51.8% compared to the transmission-gate FF.
DRNTU::Engineering::Electrical and electronic engineering