High frequency noise modeling of deep-submicron MOSFETs
Ong, Shih Ni
Date of Issue2015
School of Electrical and Electronic Engineering
GLOBALFOUNDRIES Singapore Pte Ltd.
At high frequency of gigahertz, the channel thermal noise is dominating the noise of MOSFETs. The channel thermal noise model in short channel MOSFETs deviate from long channel noise model. A simple analytical model for the high frequency channel thermal noise of deep sub-micron MOSFETs in strong inversion region is developed. The model is derived based on both the local noise source approach and the local current noise source approach, including the short channel effects, such as channel length modulation effect, velocity saturation effect, hot carrier effect and mobility reduction due to vertical field. To improve the accuracy of the channel thermal noise model especially in drain bias domain, a novel effective mobility model is developed, in which the drain-induced vertical field is incorporated. The new noise model is verified with measured results across different dimensions, frequencies, and biasing conditions. The on-wafer high frequency drain current noise characterization of MOSFETs shows a frequency-dependent trend that contradicts with the white noise assumption of the channel thermal noise. A substrate-induced drain current noise model is introduced to model the additional frequency dependent drain current noise. Y-parameter analysis is performed on the small-signal equivalent circuit of MOSFET, which includes a substrate network. A new parameter extraction technique is introduced to obtain the model parameters of MOSFET. Eventually, the total drain current noise model, including the channel thermal noise, the gate resistance thermal noise, and the II substrate-induced drain current noise, is verified with the on-wafer measurement data and is found to accurately predict the noise characteristic of MOSFETs. A gate current noise model including a newly derived short-channel induced gate noise model and the gate resistance thermal noise model is developed, followed by the corresponding cross-correlation model. Based on the proposed drain current noise model, the gate current noise model and the cross-correlation model, the four noise parameters are computed and verified with on-wafer measurement noise data.
DRNTU::Engineering::Electrical and electronic engineering::Semiconductors