Automated circuit diagram generator
Lok, Xin Quan
Date of Issue2015
School of Computer Engineering
In recent years, schools in Singapore have been encouraging students to undertake more initiative in self-learning. Self-learning allows individuals to learn at their own pace and not be restrained by their others’ learning abilities. The project is to create a program to help students in their self-learning in the area of Digital Logic, where they are able to understand the relation between a textual circuit description and its respective circuit diagram. It will help them visualise the logic circuits written textually by automatically generating a circuit diagram from it. They would be able to use the program and generate a view of the circuit diagram for their self-learning and understanding. The software approach of this project is to use Python to create a script that parses the Verilog files and generate a LaTeX TikZ (TikZ ist kein Zeichenprogramm) file, which will be a textual diagram representation of the logic circuit. An application called TeXworks is used to display the circuit diagram from the LaTeX TikZ file. There are 3 main areas in the program’s design methodology. Firstly, the parsing of the Verilog file, followed by placement and routing of components found in the file and lastly, writing the results to a LaTeX TikZ output file. The program is able to successfully generate combinational logic circuit diagrams that is written in Verilog. The program has its constraints as it is unable to handle more complex synchronous circuit written in Verilog. We will also explore on features that can be realised in order to make it more robust and practical.
Final Year Project (FYP)
Nanyang Technological University