View Item 
      •   Home
      • 1. Schools
      • College of Engineering
      • School of Electrical and Electronic Engineering (EEE)
      • EEE Theses (Open Access)
      • View Item
      •   Home
      • 1. Schools
      • College of Engineering
      • School of Electrical and Electronic Engineering (EEE)
      • EEE Theses (Open Access)
      • View Item
      JavaScript is disabled for your browser. Some features of this site may not work without it.
      Subject Lookup

      Browse

      All of DR-NTUCommunities & CollectionsTitlesAuthorsBy DateSubjectsThis CollectionTitlesAuthorsBy DateSubjects

      My Account

      Login

      Statistics

      Most Popular ItemsStatistics by Country/RegionMost Popular Authors

      About DR-NTU

      Analysis and reduction of mismatch in low power sub-threshold silicon neurons

      Thumbnail
      TeG1002555K.pdf (1.488Mb)
      Author
      Sun, Shuo.
      Date of Issue
      2012
      School
      School of Electrical and Electronic Engineering
      Research Centre
      VIRTUS IC Design Centre of Excellence
      Abstract
      In this thesis, we describe a methodical approach for reducing errors due to mismatch in neuron circuits. We chose the neuron’s current-frequency (f-i) curve as the desired output and use a sensitivity analysis to determine which transistors contribute most significantly to its variation. This allows us to identify the most critical transistors that need to be matched. For the special case in which floating-gate (FG) transistors are used to reduce this mismatch, we propose a method to further reduce the number of FG devices to be used in the circuit resulting in a corresponding reduction in ‘calibration’ time. In addition to reducing mismatch between neurons, the usage of FG devices allows the user to independently set the parameters of each neuron. Since the calibration is based on f-i curve, it can be obtained through address-event representation (AER) circuits that are included in the neuron array for normal functionality. We use one example of commonly used integrate and fire neuron to illustrate this mismatch correction procedure. The method presented allows the corrected neurons to compute both rate codes and spike time codes in a mismatch resilient fashion. We have fabricated a chip containing three different type neuron arrays, synaptic circuits, and input/output AER interfacing circuits. It occupies 2.5mmx5.5mm area using VIS 0.35um technology. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques.
      Subject
      DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
      Type
      Thesis
      Collections
      • EEE Theses (Open Access)

      Show full item record


      NTU Library, Nanyang Avenue, Singapore 639798 © 2011 Nanyang Technological University. All rights reserved.
      DSpace software copyright © 2002-2015  DuraSpace
      Contact Us | Send Feedback
      Share |    
      Theme by 
      Atmire NV
       

       


      NTU Library, Nanyang Avenue, Singapore 639798 © 2011 Nanyang Technological University. All rights reserved.
      DSpace software copyright © 2002-2015  DuraSpace
      Contact Us | Send Feedback
      Share |    
      Theme by 
      Atmire NV
       

       

      DCSIMG