dc.contributor.authorPark, Hun Sub.en_US
dc.date.accessioned2008-09-17T10:05:02Z
dc.date.available2008-09-17T10:05:02Z
dc.date.copyright2005en_US
dc.date.issued2005
dc.identifier.urihttp://hdl.handle.net/10356/5036
dc.description.abstractThe main objectives of this project are (1) to establish new test procedures for accurate wafer-level characterization of Cu electromigration behavior and low-k dielectric materials, (2) to measure the wafer-level Cu electromigration characteristics and explain them in terms of microstructural change and interfacial phenomena. The effect of copper metal lines on the device lifetime has been studied from the materials engineering point of view, (3) to study how to correlate the wafer-level reliability data with the product reliability. The wafer-level electromigration test results should be consistent with the package-level results, (4) to fully characterize a new low-k dielectric material (Black-diamond) and its influence on the electromigration reliability of the copper metal lines, (5) to identify issues arising in the integration of the backend processes, (6) to propose ideas of how to resolve integration issues resulting from the new low-k dielectric and investigate its applicability to advanced technologies.en_US
dc.format.extent140 p.
dc.language.isoen
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
dc.titleBack-end-of-line process reliability of advanced semiconductor technologyen_US
dc.typeResearch Reporten_US
dc.contributor.schoolSchool of Materials Science and Engineeringen_US


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