dc.contributor.authorKavallur Pisharath Gopi Smitha.en_US
dc.date.accessioned2011-12-27T08:27:03Z
dc.date.available2011-12-27T08:27:03Z
dc.date.copyright2010en_US
dc.date.issued2010
dc.identifier.citationKavallur, P. G.S. (2010). Low power reconfigurable digital filter banks for multi-standard wireless communications receivers. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/47495
dc.description181 p.en_US
dc.description.abstractThe fundamental idea of software defined radio (SDR) is to replace most of the analog signal processing in the transceivers with digital signal processing in order to provide the advantage of flexibility through reconfiguration. The digital front-end of an SDR employs a filter bank channelizer to extract individual radio channels from the wideband input signal. Since the filter bank operates at the highest sampling rate in the digital front-end of the receiver, low power and high-speed architectures are required for its implementation. The compatibility of a filter bank channelizer with different communication standards is guaranteed by its reconfigurability. Realizing reconfigurable channelizers with low complexity, low power and high-speed is a challenging task. This thesis addresses the research problem of incorporating low power, high-speed and reconfigurability into the filter bank channelizer architecture for the wideband receiver of an SDR.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineeringen_US
dc.titleLow power reconfigurable digital filter banks for multi-standard wireless communications receiversen_US
dc.typeThesisen_US
dc.contributor.supervisorVinod Achutavarrier Prasaden_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.degreeDoctor of Philosophy (SCE)en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record