Advanced planarization techniques for deep sub-micron applications.
Lim, Victor Seng Keong.
Date of Issue2001
School of Electrical and Electronic Engineering
In this work, the evolution of step height, film thickness and unformity, on both the STI test structures and SDRAM structure throughout the CMP process were characterized in detailed. Comparision made among the newly proposed scheme and the conventional processes such as Direct Polish (DP) Scheme and the Reverse Mask (RT) Scheme were also presented.
DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Nanyang Technological University