dc.contributor.authorSanthosh Onkaraiah.en_US
dc.date.accessioned2011-12-23T09:53:52Z
dc.date.available2011-12-23T09:53:52Z
dc.date.issued2011
dc.identifier.urihttp://hdl.handle.net/10356/46790
dc.description117 p.en_US
dc.description.abstractIncreased use of technology in day to day life for seamless activity and increased living comforts have been driving the Integrated Circuit (IC) industry to produce better hardware at cheaper and faster rate. Hence Ultra Large Scale Integration (ULSI) of ICs is accelerating to account for the need of high speed systems. Traditional scaling alone is believed to be insufficient to satisfy the interconnect performance going forward. Hence equivalent scaling using unconventional approaches would be necessary. As the scaling of integrated circuits to achieve faster, denser and smaller devices continues to drive the industry, we are at the juncture where many hurdles need to be addressed to continue on this remarkable journey of semiconductors. International Technology Roadmap for Semiconductors [ITRS] projects that the device delay is continuously scaling down but interconnect delays are increasing at a rapid rate for global and semi global interconnectsen_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleElectrical modeling of through-silicon-via for 3D integrated circuitsen_US
dc.typeThesisen_US
dc.contributor.supervisorTan Chuan Sengen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US


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