Data path allocation with interconnection optimization in high-level synthesis.
Date of Issue2001
School of Electrical and Electronic Engineering
In this thesis, a layout area estimation model based on bit-sliced standard cell design style was established. In this model, the unit area is formulated as a function of the 2-input NAND gate equivalent, and the routing track requirement is estimated using a probabilistics model.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Nanyang Technological University