dc.contributor.authorZheng, Yuhong.en_US
dc.date.accessioned2008-09-17T09:43:13Z
dc.date.available2008-09-17T09:43:13Z
dc.date.copyright2001en_US
dc.date.issued2001
dc.identifier.urihttp://hdl.handle.net/10356/4049
dc.description.abstractThis thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Power electronics
dc.titlePower optimization in data path allocation for high-level synthesisen_US
dc.typeThesisen_US
dc.contributor.supervisorJong, Ching Chuenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Engineeringen_US


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