Improvement in speed performance through transistor process optimization.
Date of Issue2003
School of Electrical and Electronic Engineering
This thesis presents the means to achieve higher speed yield for CMOS logic circuits through transistor optimization. Experiments were carried out to study the effect of each process condition on transistor drive current and its timing parameter. Based on the obtained results, selection of process conditions to achieve desired transistor drive current are presented. A linear model has been developed to predict the transistor drive current based on in-line measurement data.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Nanyang Technological University