Study of digital breakdown in pMOSFETs with ultrathin gate dielectric and its significance to reliability assessment

Abstract

The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using current-limited multiple cycle constant voltage stress tests. Samples of various dimensions are to be subjected to low voltage stresses in inversion mode and the gradual degradation of the device characteristics recorded. The evolution of the gate current, under the phenomenon of progressive breakdown, provides an insight into the evolution of the conductor-like percolation path within the oxide layer.