dc.contributor.authorYe, Xiaocheng.en_US
dc.date.accessioned2008-09-17T09:39:49Z
dc.date.available2008-09-17T09:39:49Z
dc.date.copyright2005en_US
dc.date.issued2005
dc.identifier.urihttp://hdl.handle.net/10356/3891
dc.description.abstractThe focus of this project is to study the application of new IDDQ testing schemes to deep-submicron SoC (System on Chip), for example, a 32-bit DSP microcontroller. Power partitioning has been applied to reduce the circuit scale under test from design point of view.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic systems
dc.titleIDDQ testing for deep sub-micron SOCen_US
dc.typeThesisen_US
dc.contributor.supervisorLau, Wai Shingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Microelectronics)en_US


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