De-layering of copper and low-k dielectrics for semiconductor devices failure analysis
Ng, Mei Zhen.
Date of Issue2010
School of Materials Science and Engineering
This project aims to quantify the rate of copper de-layered during Chemical Mechanical Polishing for semiconductor devices. This is to improve the effectiveness of de-layering copper during failure analysis since copper is prone to smearing, erosion and dishing. The report is generally divided into three parts. The first part begins with the description of the introduction and theoretical background of the types of techniques used in failure analysis, why copper is chosen over aluminum and the challenges faced when copper is used and failure analysis characterization. In the second part of the report, various tests parameters such as force, speed and time were deployed to characterize the polishing rates of blanket copper chip which was diced from an 8 inch copper blanket wafer. The downward force exerted on the copper chips varies from 5-15 N at a platen speed of 30 RPM for 1 minute. As for the variable speed, the platen speed varies from 30 RPM to 200 RPM at a downward force of 5 N and it is being run for 1 minute. Last but not least, keeping platen speed and downward force constant at 30 RPM and 5 N respectively, the duration of the test is varied from 1-8 minutes. Every test parameters was repeated thrice to ensure reproducibility of results collected. The thickness of the copper layer was then characterized using a Scanning Electron Microscope (SEM). However, prior to that, some sample preparations such as hot mounting, grinding and polishing were required. With the data collected and analyzed, by using a lower force of 5 N and platen speed of 30 RPM, reasonable polishing rate and relatively good surface planarity could be achieved. Furthermore, the results of these findings demonstrate some of the challenges faced during copper de-layering using Chemical Mechanical Polishing such as surface uniformity and copper smearing. Last but not least, in the third part, it will state the possible future work such as varying the slurry and polishing pad used in order to supplement the results which were derived from the earlier experiments.
DRNTU::Engineering::Materials::Microelectronics and semiconductor materials
Final Year Project (FYP)
Nanyang Technological University