Design of low power adiabatic logic circuits

Abstract

Adiabatic switching is a promising approach to realize VLSI circuit design in the area of extreme low power dissipation. It keeps the voltage drop across the switching devices small by recycling the energy that is stored at the capacitive nodes back to the power source for reuse. In adiabatic circuits, ramp-like power clock is required not only to power up the entire circuit network but also to store the recovered energy from the capacitive nodes. In this thesis, a fully dual-rail input signaling structure is adopted for the Adiabatic Pseudo-Domino Logic(APDL) family, called the APDL with dual-rail inputs (DAPDL). This logic family improves the operating frequency and the power consumption over the previous proposed family. A 4-bit shift register and a 1-bit full adder have been designed using this family. The adiabatic switching technique is also extended to the design of low power sequential circuits. Adiabatic flip-flops based on Improved PAL-2N Logic with CPL evaluation tree(C-PAL) logic family and DAPDL logic family are constructed and compared with previously proposed adiabatic flip-flops. Using the proposed flip-flops, a 4-bit counter was implemented to illustrate the cascading of sequential and combinational adiabatic logic circuits.