Realization of trenched SOI structure using wafer bonding technique.
Teo, Kim Poh.
Date of Issue2001
School of Electrical and Electronic Engineering
In this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.
DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Nanyang Technological University