Design of high performance CMOS latches and flip-flops.
Tan, Teck Heng.
Date of Issue2004
School of Electrical and Electronic Engineering
Recommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the current Chartered Semiconductor 0.18 urn and 0.25 urn CMOS technologies.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Nanyang Technological University