dc.contributor.authorTan, Ai Kiamen_US
dc.date.accessioned2008-09-17T09:27:26Z
dc.date.available2008-09-17T09:27:26Z
dc.date.copyright2002en_US
dc.date.issued2002
dc.identifier.urihttp://hdl.handle.net/10356/3325
dc.description.abstractTransistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
dc.titleResolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic deviceen_US
dc.typeThesisen_US
dc.contributor.supervisorZhang, Dao Huaen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMSC(MICROELECTRONICS)en_US


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