Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device
Tan, Ai Kiam
Date of Issue2002
School of Electrical and Electronic Engineering
Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Nanyang Technological University