Asynchronous pipelined macrocell design for high speed digital applications
Sin, Tze Yee.
Date of Issue2003
School of Electrical and Electronic Engineering
Since the beginning of the digital era, synchronous methodology has overtaken digital system design for its simplicity in implementation. The synchronous global clock, however, may become a major problem as technology scales. This rekindles the interest of asynchronous design methodology, which has long been losing its edge because of relatively more subtle design concepts and associative circuit overhead due to extra control (handshake) signaling.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Nanyang Technological University