Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures.
Goh, Wang Ling.
Tse, Man Siu.
Date of Issue2001
School of Electrical and Electronic Engineering
First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates.
DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Nanyang Technological University