dc.contributor.authorTan, Hong Mui.en_US
dc.date.accessioned2009-12-14T06:21:54Z
dc.date.available2009-12-14T06:21:54Z
dc.date.copyright1995en_US
dc.date.issued1995
dc.identifier.urihttp://hdl.handle.net/10356/19691
dc.description.abstractThe floating gate EEPROM has been a popular choice for semiconductor memories for many years. In this thesis, several areas relating to design concerns of the device have been explored. Phenomena such as charge trapping in tunnel oxide was investigated using the thin oxide MOS capacitor while device degradation was invesigaed on the EEPROM cell.en_US
dc.format.extent86 p.
dc.language.isoen
dc.rightsNANYANG TECHNOLOGICAL UNIVERSITYen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.titleDesign concerns for EEPROMen_US
dc.typeThesisen_US
dc.contributor.supervisorTse, Man Siuen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMASTER OF ENGINEERING(EEE)en_US


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