dc.contributor.authorZhu, Cheng Guo.en_US
dc.date.accessioned2009-12-14T06:20:54Z
dc.date.available2009-12-14T06:20:54Z
dc.date.copyright1998en_US
dc.date.issued1998
dc.identifier.urihttp://hdl.handle.net/10356/19671
dc.description.abstractThis Thesis looks into performance criteria such as cell loss probability, cell delay and delay jitter of different designs of ATM switches. The arrival process of ATM cells to each inlet of a switch is bursty as the traffic in the future B-ISDN can be expected to consist of compressed video and voice as well as data. Interrupted Bernoulli Process (IBP)is adopted in this Thesis to represent the input traffic. A simulation program has been developed for estimating the performance of ATM switches. Simulation for Knockout switch architecture is presented. The interrelation of the performance criteria (i.e. cell loss probability, cell delay and delay jitter), traffic characteristics, switch parameters (internal blocking and finite buffer size)and switch configuration under different operating conditions has been identified and analyzed.en_US
dc.format.extent75 p.
dc.language.isoen
dc.rightsNANYANG TECHNOLOGICAL UNIVERSITYen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
dc.titlePerformance analysis of ATM switches with bursty arrivals and finite capacityen_US
dc.typeThesisen_US
dc.contributor.supervisorTan, Chee Heng.en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMSC (COMMUNICATIONS and NETWORK SYSTEMS)en_US


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