dc.contributor.authorKoh, Christopher Seng Lee
dc.date.accessioned2009-07-02T06:53:22Z
dc.date.available2009-07-02T06:53:22Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.citationKoh, C. S. L. (2009). Accelerating the interior point method on a FPGA. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/18685
dc.description.abstractWith the dawn of reconfigurable computing, the FPGA has increasingly replaced microcontrollers as a viable alternative in the arena of embedded applications especially in DSP or high performance control applications. FPGA provides engineers the flexibility to employ significant architectural speed-up using techniques such as pipelining and parallel processing, normally not possible in off-the-shelf processors. Such customized hardware solutions however, hold the primary drawback of long development cycles. The emergence of re-configurable soft-core processors on FPGA during the past decade has changed this reality. Embedded engineers now have an additional option to build a firmware solution running on a reconfigurable microprocessor on FPGA. In addition, they also enjoy the added flexibility of using the remaining resources on the FPGA to build customized hardware-based Co-Processor or accelerators to further enhance the performance the microprocessor. A tightly coupled Co-Processor in co-existence with carefully coded firmware running on a microprocessor could effect in an improvement in performance, whilst maintaining a relatively shorter development life cycle.en_US
dc.format.extent125 p.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleAccelerating the interior point method on a FPGAen_US
dc.typeThesis
dc.contributor.supervisorLing Keck Voonen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US


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