Accelerating the interior point method on a FPGA

Abstract

With the dawn of reconfigurable computing, the FPGA has increasingly replaced microcontrollers as a viable alternative in the arena of embedded applications especially in DSP or high performance control applications. FPGA provides engineers the flexibility to employ significant architectural speed-up using techniques such as pipelining and parallel processing, normally not possible in off-the-shelf processors. Such customized hardware solutions however, hold the primary drawback of long development cycles.

The emergence of re-configurable soft-core processors on FPGA during the past decade has changed this reality. Embedded engineers now have an additional option to build a firmware solution running on a reconfigurable microprocessor on FPGA. In addition, they also enjoy the added flexibility of using the remaining resources on the FPGA to build customized hardware-based Co-Processor or accelerators to further enhance the performance the microprocessor. A tightly coupled Co-Processor in co-existence with carefully coded firmware running on a microprocessor could effect in an improvement in performance, whilst maintaining a relatively shorter development life cycle.