dc.contributor.authorChia, Hua Chew.
dc.date.accessioned2009-06-24T01:31:14Z
dc.date.available2009-06-24T01:31:14Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.urihttp://hdl.handle.net/10356/18191
dc.description.abstractSilicon nanowires (SiNWs) research has intensified over the past decade with the advancement in nanowires fabrication technology. The objective of this study is to characterize SiNWs diodes under dark and illuminated conditions to gain an understanding of the nanoscale junction devices. Two types of diodes were investigated in this project, (i) large dimension bulk diodes that served as control diodes and (ii) multiple parallel connected 1 um long SiNWs diodes. Three different batches of diodes were studied. Batch 0 demonstrated successful fabrication of SiNWs pin diodes. Batch 1 and 2 examine the formation of the nanowires, and to improve the diodes electrical characteristics. In batch 1, the silicon fin width and oxidation time were reduced and LPCVD silicon oxide was use to replace thermal oxide as passivation. Batch 2 was attempted to reduce the high leakage current observed in batch 1 diodes. This was experimented by either thermal oxide and LPCVD oxide passivation for the SiNWs. Also, the dopant activation time was reduced from 20 s to 5 s. The fabrication process is capable of producing near ideal bulk pin diodes due to the fact that the control bulk diodes have ideality factor and rectifying ratio close to 1 and twelve orders of magnitude respectively. Moreover, the forward biased current was proportional to the cross-section dimensions of the control diodes. The saturation current of batch 0 SiNWs pin diodes is around 20 fA. Such low saturation current implies high sensitivity for light sensing application. The ideality factor and rectifying ratio for batch 0 diodes are 4 and six orders of magnitude respectively whereas the ideality factor and rectifying ratio for batch 2 diodes are 1.9 and nine orders of magnitude respectively. In batch 2, the LPCVD passivated dies have higher yield. It is postulated as attributed to a stack layer of thermal/LPCVD oxide that reduces oxide defect density. Out of three methods [73], method 0 is the most suitable to extract ideality factor and series resistance from the SiNWs diodes.en_US
dc.format.extent119 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Nanoelectronicsen_US
dc.titleCharacterization and modelling of silicon nanowire based diodeen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorRusli (EEE)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeELECTRICAL and ELECTRONIC ENGINEERINGen_US


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