dc.contributor.authorWang, Gaopeng
dc.date.accessioned2009-06-18T02:54:01Z
dc.date.available2009-06-18T02:54:01Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.urihttp://hdl.handle.net/10356/17945
dc.description.abstractThis project examines various dynamic-element-matching algorithms to improve the performance of delta-sigma modulator’s multi-bit DAC due to non-idealities in circuit. Simulations at system level are performed to verify and compare the performance of those algorithms. Then one of the algorithms, data-weighted-averaging algorithm is discussed in detail and implemented at transistor-level in Cadence with the CSM018IC process. A new implementation approach for the DWA algorithm is developed and tested at circuit level. From the simulation, it is verified the designed DAC with DWA algorithm is workable at sampling frequency of 500MHz with satisfying improvement in performance compared to without DWA algorithm.en_US
dc.format.extent71 p.en_US
dc.language.isoenen_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Microelectronicsen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic systemsen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Applications of electronicsen_US
dc.titleDesign of high-speed dynamic element matching DAC for multi-bit delta-sigma modulatorsen_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorTiew Kei Teeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineeringen_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US


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