Study of stress in advanced interconnect systems (nano CMOS device and process technology)
Pey, Kin Leong.
Date of Issue2007
School of Electrical and Electronic Engineering
Several studies have illustrated that the assumption of robust SM performance of Cu is optimistic because of its strong dependency on process and structure. Stress-induced voiding (SIV) is one of the most important reliability aspects in Cu dual damascene interconnects. SIV has been a rather difficult reliability problem to address quantitatively since its first observation in 1984. Stress plays a dominant role but must be combined with other factors to understand and quantify stress migration. The purpose for this project is to develop a simulation model based on a three dimensional (3D) finite element analysis (FEA) to study the stress distribution of a gouging via. Wide bottom metal lead Cu damascene interconnects with its interconnecting Cu via gouged 400Å into its underlying metal lead was brought into the picture, and used throughout this study. Firstly, systematic studies were conducted to evaluate the stress- induced voiding mechanism under a Cu via placed over a wide metal lead from stress migration test with no electrical bias. The impact of geometrical features such as via location, metal line width and design aspects of interconnects on the stress distribution migration were studied and tested, by using the ANSYS commercial software. The effect of low-k dielectric materials on the hydrostatic stress which led to stress migration voiding inside a gauging Cu via was also analyzed. The hydrostatic stress contour plots of Cu/FSG and Cu/low-k damascene interconnect with different structure design as mentioned above were shown and the related issues were discussed. Dual-via interconnects were proven to improve SM performance. The effect of gauging via on the SM performance of Cu interconnects was also discussed.
DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics