On chip pulse based neural network for signal processing
Low, Kay Soon
Date of Issue2007
School of Electrical and Electronic Engineering
This research investigates a digital hardware oriented system that uses a genetic algorithm (GA) for optimizing a pattern classifier based on the pulsed neural network (PNN). The scheme avoids the usage of multipliers and dividers, which are the bottlenecks for digital hardware implementation of parallel computations like GA and neural networks. A new model for the pulsed neural network has been developed in this research. In this model, the information is coded in terms of firing times of pulses that are generated by the neuron. The pulses transmit through the network and excite the dynamics of the neuron. Their synchronism is utilized to design the architecture of the neural network such that it acts as a RBF network. A new network-learning algorithm has also been developed for this PNN. The RBF neurons are generated based on the feature of the training data, and the synaptic delays can be adjusted to distribute these RBF neurons in the training data space. Utilizing the nature of RBF being inherent in the pulsed neural network, the scheme yields very compact computational circuits for massive parallel implementation on a chip that guarantees the speed of neural computations. To optimize the network in real time, a hardware base GA has been developed and implemented on a FPGA. The resultant on-chip GA-PNN system has been applied for terrain classification of a multi-spectral satellite image. Experimental results show that the performance of the proposed system is comparable to a back propagation (BP) neural network while its training speed exceeds the BP network overwhelmingly. As another application demonstration, it is also extended to a nonlinear look-up table and applied to estimate the friction occurs in a precision linear stage.
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing